The present invention generally relates to information processing systems, and more particularly to an information processing system which is suited for use in a microprocessing unit and the like and enables compatibility with existing low level equipment.
In this specification, the conventionally developed information processing systems will be referred to as low level equipment. Recently, with the improved performance of computer systems, various information processing systems, which carry out the same operation as the low level equipment in response to the same instruction, have been developed. These recently developed information processing systems will be referred to as high level equipment. In other words, the high level equipment realizes the improved functions by carrying out complex operations and processing, and for example, the instruction set is extended by adding new instructions while including the same instructions used in the low level equipment.
However, when the instruction set is modified in order to realize the improved functions, the software which operates in the low level equipment may not operate in the high level equipment. For example, this situation is encountered when an instruction with which the flags for holding results of various operations do not change in the low level equipment changes to an instruction with which the flags change in the high level equipment. In such a case, there is a possibility that the software which is developed up to that time become useless.
In addition, when the emphasis is placed on compatibility of the instructions with the low level equipment by considering the effective use of the conventional software, it is impossible to make an extensive modification. As a result, it is difficult to realize improved functions and improved performance of the high level equipment. Furthermore, the development of the high level equipment lacks flexibility when the modification is restricted.
Accordingly, it is necessary to ensure compatibility of the instructions with the low level equipments when the instruction with which the flags do not change in the low level equipment changes to an instruction with which the flags change in the high level equipment by modification of the instruction set, for example.
FIG. 1 generally shows an example of a conventional information processing system. FIG. 1 shows the general structure within a microprocessor unit (MPU). An execution unit 1 functions as an operation means, and a register group 2 is made up of registers 2a, 2b, . . . , and 2z. An arithmetic logic unit (ALU) 3 functions as an operation unit for carrying out arithmetic logic operations, and a condition code register (CCR) 4 has 8 bits for storing flags indicative of states related to an operation result. An instruction decoder part 5 is made up of two instruction decoders 5a and 5b and functions as a control means. The register group 2, the ALU 3 and the CCR 4 are coupled via a data bus 6 and an address bus 7.
When developing high level equipment with respect to low level equipment in such an information processing system, the processing performance is improved by extending the instruction set, for example. The instruction set is extended by adding new instructions while including the same instructions used in the low level equipment. When actually extending the instruction set, an instruction with which the flags for holding results of various operations do not change in the low level equipment may change to an instruction with which the flags change in the high level equipment in order to realize improved functions and cope with a change in the needs. In such a case, the software compatibility cannot be maintained if the low level equipment and the high level equipment carry out different operations in response to the same instruction. Hence, the instruction decoder part 5 is formed by the two instruction decoders 5a and 5b. The compatibility of the high level equipment with the low level equipment is ensured by forming from one instruction an instruction with which the flags do not change in the instruction decoder 5a an instruction with which the flags change in the instruction decoder 5b.
Next, a description will be given of a case where the instruction with which the flags do not change in the low level equipment is modified into the instruction with which the flags change in order to realize the improved functions and cope with the change in the needs.
First, an external instruction signal is decoded in the instruction decoder part 5, and a control signal which is generated based on the decoded result is supplied to the execution unit 1 via an MPU bus (not shown). In the instruction decoder part 5, the instruction decoder 5a generates a control signal with which the flags do not change and the instruction decoder 5b generates a control signal with which the flags change. One of the control signals is selectively supplied to the execution unit 1 based on the external instruction signal. In the execution unit 1, the ALU 3 carries out arithmetic operations or logic operations based on the control signal from the instruction decoder part 5. The data which is output from the ALU 3 is stored in the register 2a which is used as an accumulator. The states related to the operation result in the ALU 3 are stored in the CCR 4.
Accordingly, two instructions, that is, the control signal with which the flags do not change and the control signal with which the flags change are generated within the instruction decoder part 5. Since one of the two control signals is selectively supplied to the execution unit 1, the high level equipment becomes compatible with the low level equipment.
However, in the conventional information processing system described above, it is necessary to provide the two instruction decoders 5a and 5b in the instruction decoder part 5 in order to maintain compatibility of the high level equipment with the low level equipment when the instruction with which the flags do not change in the low level equipment is modified into the instruction with which the flags change in the high level equipment. In other words, the scale of the hardware increases because of the need to provide the two instruction decoders 5a and 5b in the instruction decoder part 5. Therefore, there are problems in that it is difficult to reduce the cost and size of of the information processing system.